1. Field of Invention
The invention relates generally to jitter attenuation, and more specifically to apparatuses and methods for low power, small footprint jitter attenuation.
2. Art Background
A data communication system utilizes a data communication channel such as is used with Ethernet (IEEE 802.3 standard), Universal Serial bus (USB,) High Definition Multimedia Interface (HDMI,) IEEE 1394 standard (known as the Apple, Inc. product Firewire®,) etc. protocols. A data communication channel uses a clock signal to provide timing. A clock signal can be encoded together with data and transmitted from point A to point B within the communication system. When the clock is recovered at point B it can contain noise, which is referred to in the art as “jitter.” This can present a problem, since clock signals must be stable and present a waveform which does not change over time due to environmentally induced electromagnetic interference. The circuit used to remove jitter is referred to in the art as a jitter attenuator.
An existing jitter attenuator is illustrated in FIG. 1. In FIG. 1, a jittery input clock signal 104 is input to a phase detector 102. The output of the phase detector is low pass filtered by the loop filter and is input into an analog-to-digital converter (ND) 108. The output of the ND converter 108 is sent to a fractional N phase locked loop (N PLL) 110 and results in an upward or downward correction of the fractional N PLL 110 output frequency. The output of the fractional N PLL 110 is fed back at 106 to the phase detector 102. The output of the fractional N PLL 110 is either provided as clean output or is input to an output divider 114 and then output as clean output 116. The crystal 112 is located “off-chip” externally from the jitter attenuator integrated circuit die. A large die area results, power consumption is high, and cost to produce increases, all of this can present a problem.